1. Technical Field
An embodiment of the invention relates generally to the field of electronic circuits, and in particular relates to the field of voltage driver circuits.
2. Description of the Related Art
Under-driven word-lines or bit-lines are often employed in memories to accomplish full rail voltage swings with low leakage through memory access devices. In particular, dynamic random access memory (DRAM) designs employ under-driven word-lines to improve the retention time of storage cells by cutting down leakage through the pass transistors. For instance, with a pass transistor being employed to drive a word-line in a DRAM to Vcc, the gate of the pass transistor may be driven beyond the positive power supply rail of Vcc, strongly cutting off the pass transistor so that the word-line will not leak charge back through the pass transistor. With a higher voltage on the gate of the pass transistor than on the source (drain), leakage back through the pass device is virtually eliminated. However, the higher voltage may exceed the breakdown voltage of the individual transistors being used to drive the pass transistor. This problem is typically handled by cascode voltage switch logic (CVSL) using cross-coupled PMOS pull-up devices, and NMOS pull-down devices to cause the cross-coupled PMOS devices to switch. However, the CVSL logic typically has slow switching speeds because the pull-down NMOS devices must overcome the output of the PMOS devices to cause the output to transition. Slow switching speeds are an impediment to improving memory access times.